This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2000-351787, filed on Nov. 17, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to semiconductor memory integrated circuit (IC) devices configured using memory cells of the current readout type.
2. Description of Related Art
Currently available memory cells adaptable for use in semiconductor memory IC devices include those cells of the type performing data storage depending upon whether a current flowing during cell selection is present or absent or alternatively whether such current is large or small in amount. This type of memory cells will be referred to hereinafter as the xe2x80x9ccurrent-drivenxe2x80x9d type memory cells in the description. Known current-driven memory cells include non-volatile memory cells suitable for use with electrically programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM) chips, which cells are of the multilayered gate type metal oxide semiconductor (MOS) transistor structure having a floating gate or alternatively the metal nitride oxide semiconductor (MNOS) transistor structure, the metal oxide nitride oxide semiconductor(MONOS) transistor.
Other known memory cells include magnetic random access memory (MRAM) cells employing magnetoresistance (MR) effects, thyristor-RAM (T-RAM) cells using negative differentiation resistance each formed of a thyristor and a select transistor (such as disclosed in F. Nemati and J. D. Plummer, 1996 Symp. on VLSI Tech. at pp. 66-77, as will be referred to as xe2x80x9cDocument #1xe2x80x9d or simply xe2x80x9cD1xe2x80x9d in the rest of the description), tunnel switch diode (TSD) cells using TSDs (as recited for example in H. J. Levy et al., IEEE Journal of Solid-State Circuits, vol. 33, April 1998, pp. 669-672, to be referred to as xe2x80x9cDocument #2xe2x80x9d or xe2x80x9cD2xe2x80x9d hereafter), and a specific type of dynamic random access memory (DRAM) cells called xe2x80x9cgain cellsxe2x80x9d among those skilled in the semiconductor memory art. The gain-cell type DRAM cells are generally categorized into the two: the one that stores a packet of electrical charge carriers while using the gate of a sensing MOS transistor as its storage node, and the other that is designed to utilize the so-called xe2x80x9cbackgate biasxe2x80x9d effect for storage of electrical charge with the bulk region (channel body) of a sense MOS transistor being used as the storage node thereof.
In the case of memory cells of the floating gate type for general use in EPROMs and EEPROMS, data determination or xe2x80x9cjudgmentxe2x80x9d is done by detection of a difference of drain current in view of the fact that the threshold voltage is different depending upon the amount of electrical charge being presently accumulated at the floating gate of interest. It should be required at this time that a drain voltage be suppressed at a low potential level for preclusion of unwanted occurrence of writing during reading. Typical examples of prior known sense amplifier circuitry used in EEPROMs are shown in FIGS. 55 and 56.
The sense amplifier system shown in FIG. 55 is the one as taught by N.Ohtsuka et al., xe2x80x9cA 62 ns 16 Mb CMOS EPROM with Address Transition Detection Technique,xe2x80x9d ISSCC Digest of Technical Papers, February 1991, pp. 262-263. The sense amp system of FIG. 56 is disclosed in G. Canepa et al., xe2x80x9cA 90 ns 4 Mb CMOS EPROM,xe2x80x9d ISSCC Digest of Technical Papers, February 1988, pp. 120-121. Note here that the both circuits are shown so that portions less relevant to this invention are eliminated from the illustrations.
The sense amp circuits of FIGS. 55-56 are both designed to perform an operation for establishment of a specific bitline voltage potential as determinable by load-to-memory cell ratios in turn-on resistance values thereof, also known as xe2x80x9cratioxe2x80x9d operation among those skilled in the art to which the invention pertains; thus, a bitline potential changes from 0.5 V to 1V or more or less in a way pursuant to the threshold voltage level of a memory cell. Electrons are accumulated at the cell""s floating gate, causing a bit line associated with a memory cell of higher threshold voltage (and thus the cell""s drain) to potentially go high. The remaining, non-selected memory cells are such that their word line-coupled control gates are kept at 0V; thus, if the drain potential is high then electrons are readily injectable thereinto. The presence of this high drain potential can cause writing errors, especially for those memory cells presently in an erase state (ordinarily, logic data xe2x80x9c1xe2x80x9d storage state).
In the case of multiple-value data storage, a four-value storage scheme based on a threshold value distribution shown for example in FIG. 35 is representatively known, which is found in M.Bauer et al., ISSCC95 at pp. 132-133. One typical sense amplifier circuitry suitable for use in the case of such multi-value storage is configured as shown for example in FIG. 56, which is suggested from M.Bauer et al., xe2x80x9cA Multilevel-Cell 32 Mb Flash Memory,xe2x80x9d ISSCC Digest of Technical Papers, February 1995, pp. 132-133. Here also, any part irrelevant to this invention is eliminated from the illustration.
As in the case of two-value storage, the sense amp circuit shown in FIG. 56 is designed to do the xe2x80x9cload-to-cell turn-on ratioxe2x80x9d operation discussed above. Accordingly, in accordance with a present threshold voltage of a memory cell, its associated bit line potentially increases from 0.5V and then goes beyond 1V. In addition, the required sense time period is longer than that of the two-value storage due to the fact that upper and lower level data bits are read out sequentially-that is, the upper level data bit is first read and thereafter the lower bit is read out. Even when word-line closing control is done after completion of each bit data reading, possible stress becomes stronger when compared to the two-value case, resulting in the circuitry suffering from high risks of writing errors.
MRAM cells also include memory cells of the type utilizing magnetic tunnel junction (MTJ) architectures, called xe2x80x9cMTJ-MRAMxe2x80x9d cells, examples of which are disclosed in R.Scheuerlein et al., 2000 ISSCC at pp. 128-129 (xe2x80x9cDocument #3xe2x80x9d or xe2x80x9cD3xe2x80x9d) and M.Durlam et al., 2000 ISSCC, pp. 130-131 (xe2x80x9cD4xe2x80x9d). These MTJ-MRAM cells taught thereby utilize the fact that electrical resistance when spins of ferromagnetic materials with an interposed tunneling dielectric film forming an MTJ are parallel in direction is different in value that when the spins are anti-parallel (the resistance is large when spins are antiparallel). With such MTJ-MRAM cells, a resistance difference becomes smaller with an increase in voltage to be applied to the MTJ; thus, it is required that any application voltage be suppressed in potential. Although the resistance difference gets larger owing to research and development results in recent years, the application voltage is strictly required to fall within a limited range of from 0.2 to 0.4V; otherwise, the resistance different would decrease thereby making the data judgment more difficult.
A basic structure of MTJ-MRAM cell is shown in FIG. 33A, and equivalent circuitry of it is depicted in FIG. 33B. Also see FIG. 34, which shows a relation of the MTJ-MRAM cell""s resistance change versus a bias voltage used, sometimes called the xe2x80x9cbias voltage-dependent resistance change characteristic,xe2x80x9d as taught by M.Durlam et al., xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elements,xe2x80x9d ISSCC 2000 slide supplement, February 2000, pp. 410-411. As shown in FIG. 33A, the MTJ-MRAM cell is designed so that its MTJ is formed of ferromagnetic films 331, 333 with a tunnel dielectric film 332 sandwiched therebetween. The lower ferromagnetic film 331 is spin-fixed whereas the upper film 333 is spin-variable. The upper ferromagnetic film 333""s spin drive is done by use of a bit line BL and a write-use word line W-WL, which lines run at right angles to each other with the MTJ interposed therebetween. The MTJ is grounded through a select transistor QS, which is driven by a read-use word line R-WL. In view of the fact that the MTJ differs in resistance in a data-dependent way, MTJ may be represented equivalently as a variable resistor VR as shown in FIG. 33B.
A configuration of sense amplifier circuitry adaptable for use with the MTJ-MRAM cells is shown in FIG. 53 (see the above-identified document D3). This sense-amp circuit shown herein also is designed to perform the xe2x80x9cload-to-cell ratioxe2x80x9d operation stated previously. With such operation, an application voltage to certain MTJ increases in potential if the MTJ is high in resistance and antiparallel in spin direction, which would result in a decrease in change of resistance causing a resistance difference relative to a spin-parallel MTJ to likewise decrease, as suggested by the data of FIG. 34.
The prior art memory cell structures of the above documents D3 and D4 are arranged so that a 1-bit cell is made up from a couple of transistors plus two MTJ elements, for writing complementary data bits into the MTJ elements. With such xe2x80x9c2-transistor/2-MTJxe2x80x9d cell configuration, a readout signal is significant. Unfortunately, this does not come without accompanying a trade-off: the use of many elements for each cell suffers from reduction of on-chip integration density and per-cell storability; if a 1-transistor/1-MTJ cell structure is employed for achieving mass-storabilities, then, a reference voltage must be set at a potential level as created by an intermediate resistance that is midway between the resistance values of a spin-antiparallel MTJ element and that of spin-parallel MTJ element, resulting in a read signal amount becoming half-reduced. Thus a need is felt to avoid the use of any application voltages with risks of resistance difference reduction.
In the case of a TSD cell of the metal insulator semiconductor (MIS) switch diode type, this is structured as shown in FIG. 28A and is represented by a symbol shown in FIG. 28B. More specifically, this cell structure is such that an insulated gate electrode (anode electrode) is formed over a p-type semiconductive layer of a p-n junction diode with a tunnel dielectric film sandwiched between them. The TSD has two terminals, one of which is capable of enlarging a read current if a higher voltage is applied thereto. Unfortunately as shown in a characteristic diagram of FIG. 29, upon occurrence of excessive potential rise-up beyond a trigger voltage Vpeak entering a negative differential resistance region, read errors can occur causing a read voltage VR to be limited.
Although the above-identified document D2 with teachings about TSD cells is silent about any specific sense-amp circuitry, a scheme is employable for performing reading through execution of a TSD-cell to load ratio operation with a common load provided at a single bit line; if this is the case, the bit-line potential can decrease when a large current flows into the TSD, resulting in a decrease in voltage being applied between the electrodes of TSD, which in turn leads to loss of a drive current. Alternatively if the TSD cell is potentially increased at its anode then a voltage across the electrodes of one TSD cell less in current flow will possibly go beyond the trigger voltage Vpeak in some cases.
According to the document D1, a T-RAM cell with a thyristor used as its storage element is structured as shown in FIG. 30A with a symbol shown in FIG. 30B used to represent the T-RAM cell. The thyristor here is a xe2x80x9cpnpnxe2x80x9d thyristor TH having its p-base with a sidewall, on which a word line WL2 of MOS gate structure is formed to have a ring-like shape. This thyristor TH has an n-emitter which is connected to a bit line BL via a select MOS transistor QS controllable by a word line WL1. This T-RAM cell is also capable of increasing a read current with use of larger voltages. See FIGS. 31A and 31B, the former of which shows a current versus voltage characteristic of the T-RAM cell during data holding, and the latter of which shows a characteristic during data reading. Exceeding beyond the trigger voltage Vpeak entering the negative differential resistance region can cause read errors; thus the read voltage VR is limited. This is similar to that of the TSD cell stated supra. Although D1 with teachings of T-RAM cells fails to suggest sense-amp circuitry per se, execution of the ratio operation would cause similar problems to those in the case of TSD cells.
Presently available gain cells using the gate of a sensing MOS transistor as its storage node for electrical charge accumulation include phase-state low electron-number drive RAM cells, also known as xe2x80x9cPLEDMxe2x80x9d cells, one of which is disclosed in K.Nakazato et al., xe2x80x9cPhase-state Low Electron-number Drive Random Access Memory (PLEDM),xe2x80x9d ISSCC Digest of Technical Papers, February 2000, pp. 132-133(xe2x80x9cD5xe2x80x9d). The structure of such PLEDM cell is illustrated in FIG. 36A, and its equivalent circuit is shown in FIG. 36B.
A heavily-doped n (n+) type gate electrode of sense MOS transistor Q1 is for use as a storage node Vn with its drain being connected to a read bit line BL-Read. A multilayer structure with alternate lamination of silicon nitride films and i-type silicon films is over the gate electrode. A write bit line BL-Write is formed on the multilayer structure. This bit line may be an n+ type silicon layer. A word line WL is formed to cover these components making up the gate structure, with a dielectric film interposed therebetween. Interlayer part of the storage node Vn and write bit line BL-Write constitutes a write MOS transistor Q2 of the vertical type, which is extremely less in current leakage. With such a structure, a gain cell is obtained.
An operation condition indicated in Document D5 is as shown in FIG. 37A. Sense amplifier circuitry is configured as shown in FIG. 57. Data writing is performed in such a way that either H level (for example, 1.5V for a data bit of logic xe2x80x9c1xe2x80x9d) or L level (e.g. 0V for data xe2x80x9c0xe2x80x9d) is written into the storage node Vn through the write MOS transistor Q2 while substantially simultaneously applying to word line WL an H-level write potential (e.g. 3V). In a standby state, a negative potential (xe2x88x922V) is given to word line WL causing storage node Vn to potentially stay at or below the threshold voltage of sense MOS transistor Q1 due to the presence of a coupling capacitor Cc between word line WL and storage node Vn. Data read is done by giving to word line WL a read voltage potential of about 0.5V to thereby drive sense MOS transistor Q1 to turn on only when H level is held at storage node Vn.
It is demonstrated by D5 that the storage node is at about xe2x88x922V in case a logic xe2x80x9c0xe2x80x9d has been written or xe2x80x9cprogrammedxe2x80x9d into non-select cells (i.e. a built-in capacitor shown in FIG. 37B is of 0.04 fF), and also that a potential difference of 3.5V is available between the gate and drain of a non-select cell-associated sense MOS transistor Q1 upon precharging of read bit line BL-Read at 1.5V, or more or less. As integration densities decrease due to rapid growth of semiconductor microfabrication technologies, the channel length of sense MOS transistor Q1 is shortened; if this is the case, its gate oxide film is ordinarily made thinner for suppression of short-channel effects. One example is that if electric fields being applied to the gate oxide film are limited to 5 MV/cm then this film is required to measure as thick as 7 nanometers (nm), resulting in the channel length being merely scaled down to 0.25 xcexcm.
The same discussion will not automatically be applicable to other types of gain cells with sense MOS transistor gates used as storage nodes, it is true that sense MOS transistors of the virtually floating gate type must be employed in cases where write MOS transistors are less in current leakage with storage nodes being small in capacitance (these are inevitable for microfabrication of gain cells of the type accumulating electrical charge with sense transistor gates used as storage nodes). As far as such architecture is used, even if charge carriers as injected into a gate due to drain avalanche with application of a potentially high drain voltagexe2x80x94xe2x80x9chotxe2x80x9d carriersxe2x80x94are less in amount, resultant storage node potential change is significant undesirably.
Additionally, with the sense-amp circuitry shown in FIG. 57, even when such drain avalanche does not occur, those non-select cells satisfying the above-noted biasing conditions can experience bit-line precharge voltage reduction due to the presence of gate potential-induced drain current leakage, also known as the gate induced drain leakage (GIDL). This precharge voltage reduction causes read errors in some cases. In other cases, the same would result in writing being done at a storage node with low voltages because of the fact that a bit-line precharge voltage is for direct use as a write voltage for restoring.
Further, turning back to the discussion on the read operation, sense MOS transistors of the load and gain cell are designed to perform the ratio operation, although the sense-amp circuitry of FIG. 57 per se does not offer any ratio operability. If this is the case, it is required that the sense MOS transistors be low in drain voltage; otherwise, injection of those electrons without experience of any collisionxe2x80x94say, lucky electronsxe2x80x94into storage nodes can occur due to hot carriers, as in EPROMs. Thus it is desired that the sense MOS transistors be lowered or minimized in drain voltage.
A typical one of gain cells of the type utilizing the backgate bias effects with sense MOS transistor bulk (channel body) regions as storage nodes thereof is a capacitor-less DRAM (CDRAM) cell, as disclosed in H.Wann and C.Chu, xe2x80x9cA Capacitorless DRAM Cell on SOI Substrate,xe2x80x9d IEDM Digest of Technical Papers, Dec. 1998, pp. 635-638(xe2x80x9cD6xe2x80x9d). A CDRAM cell structure is shown in FIG. 38A, with its equivalent circuit depicted in FIG. 38B.
The CDRAM cell shown is generally formed of a sense-use P-channel MOS (PMOS) transistor Q1 and a write N-channel MOS (NMOS) transistor Q2 over a silicon-on-insulator (SOI) substrate, these transistors having a common gate. The sense PMOS transistor Q1 has its source connected to a read-use bit line BL-Read and an insulated channel body of n+ type for use as an electrically xe2x80x9cfloatingxe2x80x9d storage node. The sense PMOS transistor Q1 has its p+ type drain coupled to a purge line PL. Arranged between the storage node and a write-use bit line BL-Write is a write NMOS transistor Q2 with a region of purge line PL used as the channel body. With such a structure, the gain cell is thus obtained.
Operation voltages of the CDRAM of Document D6 are as shown in FIG. 39. An H-level voltage is applied to word line WL for writing H or L level into the channel body of sense PMOS transistor Q1 through NMOS transistor Q2. Then a negative voltage is given to purge line PL to thereby hold data. Reading is done by detection of a change in bit-line potential based on turn-on or off of sense PMOS transistor Q1 while applying negative voltage to purge line PL and also giving a 0-V voltage to the word line.
Although D6 lacks any detailed explanation about sense circuitry, the cell structure also must undesirably satisfy the hot-carrier injection conditions if the drain voltage is high in potential for holes, judging from the fact that the cell as taught thereby is designed so that the channel body is used as the storage node.
As apparent from the foregoing discussions, prior art semiconductor memory devices using current-driven memory cells with limited bias conditions are such that a bitline clamping potential is determined by execution of the so-called load-to-memory cell ratio operations under control of load currents with respect to memory cells. The use of such architecture is faced with a problem as to unwanted increase in stresses being applied to the memory cells. If an attempt is made to lessen such stresses, the resultant memory cells are no longer capable of sufficiently offering the performance required.
The magnetoresistive memory device in accordance with one aspect of this invention comprises more than one memory cell storing data therein depending on whether its magnetoresistance is large or small in value and a sense amplifier connected to a bit line from which data of the memory cell will be output for detecting or sensing the data of the memory cell, wherein the sense amplifier includes an operational amplifier which has its inverting input terminal connected to the bit line and a non-inverting input terminal with a fixed potential applied thereto, and a clamping transistor being under feedback control in response to an output of the operational amplifier for forcing the bit line to be clamped at the fixed potential without regard to any data being read, the transistor having its drain connected to the inverting input terminal and a source coupled to an output terminal of the operational amplifier.